Google To Develop Its Own Mobile Chip For 2021 Pixel Phones

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Google is all set to develop its own chip for Pixel and Chromebook devices. As per a report, the global tech giant will be working with Samsung to develop custom chips for Pixel devices, which are codenamed as Whitechapel. With the assistance of 5-nanometer technology, Google will be manufacturing the chip. If not in 2020, we are assuming that the chip will be introduced by next year. If the development turns out to be successful, it will surely give a blow to Qualcomm, which is the current supplier to Google for all Pixel phone chips.

As per the report published by Axios, Google has already started working rigorously on it and has created few versions that will be integrated in the Pixel device by next year. The chip is named as Whitechapel and it includes an eight-core ARM processor. The chip will also include hardware that is optimised for Google’s machine-learning technology. The report further informs that the chip will have its own dedicated space for improving the performances and capabilities of the Google Assistant.

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As mentioned earlier, the company has partnered with Samsung and has simultaneously manufactured Apple’s A-series chips as well. Google has plans to make the same chip for Chromebook after the company successfully implements it in the Pixel devices. A lot of important points matter when one makes a mobile processor and this time Google has to ensure that it can succeed in all its endeavours to be able to compete with Apple. The Cupertino giant uses its own A-series Bionic chips inside the iPhone models.

A report from Korea suggested that the chip will probably come with eight CPU cores coupled with four Cortex-A55, two Cortex-A78 cores, and two Cortex-A76 cores. As per the report, Samsung has stopped using its image signal processor (ISP) along with neutral processing unit (NPU) and is using Google’s visual core and the search giant’s NPU instead. This chip is also rumoured to feature ARM’s unannounced Mali MP20 GPU which depends on Borr microarchitecture